1. Field of the Invention
The present invention relates to a non-volatile memory such as a NAND flash memory. In particular, the present invention relates to a semiconductor memory, which can repair a defective bit before and after shipment, and to a semiconductor memory system.
2. Description of the Related Art
Recently, a bit capacity of a non-volatile memory rapidly increases with advance in a semiconductor refinement technique. For this reason, according to a memory chip screening test, a large number of defective products (memory chips) are generated. This is because the screening test is made on the premise that all bits of a memory are non-defective in manufacturing. As a result, it is difficult to secure sufficient yield. Therefore, the following various defective bit redundancy techniques are practically employed so that a memory chip having minor defective bits is used as a non-defective chip.
(1) Redundancy Technique of Repairing Defective Bits in a Memory Chip
The following techniques are given as the redundancy technique. One is a column redundancy technique of replacing a defective column with a non-defective column. Another is a block redundancy technique of replacing a defective block with a non-defective block. Hereinafter, simultaneously erasable areas call an erase block, and the erase block unit is referred to simply as block. One block includes a plurality of pages as a write/read unit. Each page comprises a plurality of memory cells.
(2) Defective Bit Redundancy Technique Executed by a Controller Built in a Non-Volatile Memory
The following techniques are given as the defective bit redundancy technique. One is an error correction technique using an Error Check and Correction (ECC) circuit. Another is a defective column skip technique of skipping a defective column, and replacing the defective column with a normal column. Another is a defective block replacement technique of replacing a defective block with a normal block.
(3) Memory Chip Test Technique
A pseudo-pass technique is given as the test technique (For example, see Jpn. Pat. Appln. KOKAI Publication No. 2002-140899). According to the pseudo-pass technique, correction by the ECC circuit is set force as a premise, and even if minor defective bits exist in a page, this is disregarded so that the page is passed as a pseudo-normal page.
Of the techniques, the ECC technique is specifically effective as the defective bit redundancy technique, and has the following features. According to the features, if an increase of a circuit scale is allowed, a design of an ECC circuit is flexibly made in accordance with intensity of required error correction.
According to the pseudo-pass technique, defective bit correction by the ECC technique is set force as a premise. In this way, the yield of memory is largely improved. A correction unit by the ECC circuit (referred to as ECC unit) is 512 bytes, for example. A 4-bit/512 byte ECC technique is set force as a premise. The 4-bit/512 byte ECC technique can correct four defective bits or less of the ECC unit. Based on the ECC technique, a two-bit pseudo-pass technique is practically used. According to the two-bit pseudo-pass technique, even if two defective bits exist per one page (2 Kbytes=2048 bytes), the page is passed as a normal page.
Recently, a non-volatile memory built in a memory card has the following tendency. According to the tendency, the number of writable/readable bits in one time=page size rapidly becomes large to meet the requirements of high speed. Conventionally, a 130-nm-generation NAND flash memory has 512 bytes per page (small block). However, a 90-nm-generation NAND flash memory has 2 Kbytes per page (large block). In future, there is a likelihood of the NAND flash memory having 4 or 8 Kbytes per page. For this reason, the ECC circuit has a tendency for the number of bits corrected in one time to increase. However, the ECC circuit has a problem that as the ECC unit becomes larger, the circuit scale rapidly increases. Thus, in a 70-nm NAND flash memory, one page (2 Kbytes) is divided into four 512-byte portions, and then, correction by the ECC circuit is made four times. Further, there is a tendency for a gap between the page size and the ECC unit to become large more and more.
For example, the number of defective portions (defective bits) correctable by the ECC circuit is set as X, and defective portions disregarded by the pseudo-pass technique is set as Y, and further, one page is divided into Z ECC units to make corrections. In this case, even if M defective portions concentrates on one ECC unit, the correction ability by the ECC circuit is limited; therefore, the following equation (1) is established.X≧M   (1)
Here, a relation of α=X−M is set. In this case, α is the number of later allowable defective bits. Specifically, α is the allowable number of defective bits generated later after a screening test is made before shipment of a non-volatile memory, and is margin of the number of defective bits. When α=0, if one defective bit is generated later, this exceeds correction ability by the ECC circuit; as a result, a memory system falls in a dangerous state. For this reason, α=0 is not set considering the use of the memory system, data retention intensity, for example, degradation of a memory cell by repeatedly making write and erase with respect to the memory cell. Therefore, as seen from the following equation (2), defective portions Y disregarded according to the pseudo-pass technique is set under the condition that the number α of allowable defective bits generated later is 1 or more.Y=X−α, α≧1   (2)
In the 70-nm multi-level NAND flash memory, the following parameters are practically used. Specifically, Z=4 (page size: 2 KB/ECC unit: 512 bytes, Y=2 (2-bit pseudo-pass), X=4 (4 bits/512 bytes redundancy), and α=2.
As described above, there is a tendency for page size and ECC unit to become large more and more in future. The difference between the page size and the ECC unit becomes large, and thereby, the following problem arises. Specifically, the upper limit of the number of allowable defective bits according to the pseudo-pass technique is defined by the equation (2). However, as the difference between the page size and the ECC unit becomes large, namely, as the ECC unit number Z become large, the following probability that M defective bits all concentrate on one ECC unit in one page rapidly becomes small. In other words, the upper limit of the equation (2) is the upper limit of M portions that correction by the ECC circuit is secured in the worst case having a very low generation probability. In fact, in most of cases, M defective portions properly disperse in Z ECC units. For this reason, even if M portions exceeding the equation (2) exist, correction is sufficiently made by the ECC circuit correcting X portions. Therefore, according to the conventional pseudo-pass technique, a non-volatile memory chip, which is still sufficiently usable as a non-defective product, is determined as a defective product. Thus, it is desired to provide a semiconductor memory and a semiconductor memory system, which can further improve the yield.